Multiprocessor Arbitration for AMBA Interface in ASIC

Abstract

This paper addresses the multiprocessor arbitration for any System on Chip or ASIC. Any system, be it a simple controller or a very supplicated system, it needs a processor to operate. There are series of processors offered by Intel, AMD or processor companies. The previously single processor was used for any chop to access different targets. But technology advances, the industry felt the need for multiprocessor access for higher performance. To allow multiprocessor to access its targets, the system needs an efficient interface with a very sophisticated arbitration system. This paper researched to develop an improved hardware algorithm to allow multiprocessor access to the system. To design the hardware, a modern HDL based design methodology has been used. There are two industry-standard HDL by IEEE – VHDL and Verilog. Here Verilog is used. In HDL based d=hardware development, simulation is the most important part to verify the design’s functionality and make sure it is 100% correct. Otherwise, if any design problem goes forward undetected, that’ll cost so much money and time to go back and fix, in some cases, full respin. For hardware implementation, Xilinx FPGA Device has been targeted in this research. AMBA bus protocol used in this research is the industry-standard protocol for processor access and is very efficient and straightforward to use with any off the shelf macro available for the high-tech industry.