Multiprocessor Arbitration for AMBA Interface in ASIC
Keywords:Multiprocessor Arbitration, AMBA Bus Protocol, Processor Interface, FPGA, ASIC
This paper addresses the multiprocessor arbitration for any System on Chip or ASIC. Any system, be it a simple controller or a very supplicated system, it needs a processor to operate. There are series of processors offered by Intel, AMD or processor companies. The previously single processor was used for any chop to access different targets. But technology advances, the industry felt the need for multiprocessor access for higher performance. To allow multiprocessor to access its targets, the system needs an efficient interface with a very sophisticated arbitration system. This paper researched to develop an improved hardware algorithm to allow multiprocessor access to the system. To design the hardware, a modern HDL based design methodology has been used. There are two industry-standard HDL by IEEE – VHDL and Verilog. Here Verilog is used. In HDL based d=hardware development, simulation is the most important part to verify the design’s functionality and make sure it is 100% correct. Otherwise, if any design problem goes forward undetected, that’ll cost so much money and time to go back and fix, in some cases, full respin. For hardware implementation, Xilinx FPGA Device has been targeted in this research. AMBA bus protocol used in this research is the industry-standard protocol for processor access and is very efficient and straightforward to use with any off the shelf macro available for the high-tech industry.
P. Giridhar and. P. Choudhury, “Design and Verification of AMBA AHB,” 1st International Conference on Advanced Technologies in Intelligent Control, Environment, Computing & Communication Engineering (ICATIECE), 19-20 Mar 2019, India.
H. Saluja and N. Grover, “Multiple Master Communication in AHB IP using Arbiter,” International Journal of Engineering and Manufacturing (IJEM), vol. 10(1), pp. 29-40, 2020.
L. Deekhsa and B. R. Shivakumar, “Effective Design and Implementation of AMBA AHB Bus Protocol using Verilog,” 2019 International Conference on Intelligent Sustainable Systems (ICISS), 21-22 Feb 2019, Palladam, India.
J. Tu and C. Ou, “A practice of 2-to-2 fixed priority arbiter used to multi-core processors,” International Conference on Applied System Innovation (ICASI 2017), 13-17 May 2017, Sapporo, Japan.
A. Mishra, “Design of a Round Robin Bus Arbiter using System Verilog,” International Research Journal of Engineering and Technology (IRJET), vol. 7(1), pp. 29-40, 2020.
A. A. K. Qahtan and A. M. A. El-Kustaban, “A Bus Arbitration Scheme with an Efficient Utilization and Distribution,” International Journal of Advanced Computer Science and Applications ((IJACSA 2017), vol. 8(3), pp. 1-6, No. 2017.
M. I. R. Rokon, S. M. A. Motakabber, M. Hadi Habaebi, A. H. M. Zahirul Alam, M. A. Matin, “Smart Arbitration System for Multiprocessor AMBA Interface in System on Chip”, 2021 8th International Conference on Computer and Communication Engineering (ICCCE).
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The Asian Journal of Electrical and Electronic Engineering journal is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.